Popcorn Testing of Liquid Encapsulants
John Barton, Richard Murphy, Rory Doyle, Kieran Delaney, NMRC, Lee Malting, Prospect Row, Cork, Ireland, Phone: +353 21 904088, Fax: +353 21 270271, E-mail: jbarton@nmrc.ucc.ie, Inpact Microelectronics, Phone: + 353 21 4318296, Fax: +45 4465 1458, E-mail: rory.doyle@inpactmicro.com
Abstract
Glob-top encapsulation has found wide-spread acceptance in electronics assembly for low-end, consumer products. To extend the use of this encapsulation method to high reliability and harsh environment conditions, a rigorous evaluation of the available materials is needed. This paper outlines the results of popcorn tests on a wide range of liquid encapsulant materials. The materials were chosen on the basis of being market leaders in providing reliable protection for direct attached ICs and are used in several applications such as glob-top for COB through to IC protection in BGA and multi-chip style packaging. Evaluations based on variables such as encapsulant type, substrate material and wire-bond material were performed to compare these encapsulants. Electrical characterization and non-destructive scanning acoustic microscopy were the main analysis techniques used on the samples.
Key words: encapsulant, failure analysis, glob-top, reliability, scanning acoustic microscopy
Introduction
NMRC has carried out extensive testing of several commercially available glob-top encapsulants. The trials were targeted at assessing glob-top encapsulants as a viable means of packaging ICs in high reliability applications. The materials used were chosen on the basis of being market leaders in providing reliable protection for direct attached ICs and are used in several application such as ‘glob-top’ for chip-on-board (COB) through to IC protection in BGA and multi-chip style packaging.
Recent improvements in encapsulant product quality and performance have prompted studies to determine the ability of these materials to provide high reliability chip protection[1]. Investigations to compare material types and develop quality assessment methods have reported on potentially high reliability products[2]. The ability of glob-tops to successfully encapsulate large area chips has also been investigated[3].
This project has been prompted by the wide selection of such materials on the market and the high cost to individual companies to evaluate their suitability. The large variety of material and process options makes the choice of suitable materials a time consuming and expensive task.
A range of common assembly variables has been included in these trials to study the implications of the many manufacturing choices available. These variables include the interconnection substrate material (FR4/BT), wire bond material (Al/Au) and wire bond loop geometry. A total of eight epoxy and silicone encapsulant products have been included in the material set.
Material Selection
Encapsulants were required to be dispensed using an automated dispense unit and be capable of encapsulating to a height of 1.5 mm. Following initial selection, suppliers of each encapsulant were contacted and advice sought as to the suitability of this choice. Many suppliers recommended their most recent variants of the selected encapsulants. Following this advice the final selection of encapsulants was made. Five epoxies and three silicones were selected for the study.
Details for each encapsulant is given in table 1 overleaf.
Test IC
The test strategy used in the project was designed around the NMRC’s PMOS 4 Package Performance Monitoring Test Chip. This general purpose, 5mm X 10mm, package monitoring test chip contains test structures to evaluate several IC package performance parameters. Two of these test structures are used in this project, triple track meander corrosion monitors and daisy chain wire bond structures.
To evaluate the encapsulant’s ability to protect against external corrosive effects and also to monitor any corrosive effects the encapsulant has on the test chip, triple track corrosion monitors are used. By biasing the meanders (centre track ground and the outer tracks biased + and - 5 volts), the occurrence of electro-chemical corrosion of aluminum can be observed by monitoring both the increase in leakage current and also the changes in the track resistance.
To investigate wire bond reliability for each encapsulant, a daisy chain bond pad structure was used for each of the encapsulants. Daisy chain structures allow for a continuous array of over 60 wire bonds around three sides of the PMOS4 chip. This chain is tapped with test points at each wire/board junction to enable precise monitoring of the effects on each encapsulant over the course of the environmental stress tests. To maximize the overall length of the daisy chains and to observe the corrosion effects over a large area, two “multi-up” PMOS4 chips are used to form a 10mm x 10mm chip.
Test Board
The design of the test board needed to satisfy the following requirements for this project.
- Provide a robust and workable board for assembly requirements.
- Suitability for both Gold and Aluminum wire bonding.
- Provide three different wire bond lengths/geometry’s.
- Accurate and repeatable PMOS4 IC placement.
- Enable external observation of the corrosion monitors and the daisy chains.
- Provide sufficient surface area for encapsulation of the PMOS4 chip.
- Enable external biasing of the corrosion monitors.
- Easily and automatically testable.
The connection to the IC corrosion monitors and the daisy chains was through a series of 150µm wire-bond pads situated around the PMOS4 chip with tracks leading from them to 0.1 inch pitch finger edge connectors.
The schematic layout of the board is shown in Figure 2 while a picture of an FR4 test board is shown in Figure 3. To accommodate both Aluminum and Gold wire-bonds, the bond sites on the test board are plated with 3µm of soft gold. The bond points are also located approximately 1, 2 and 3mm from the chip to observe the effects the encapsulant has on various wire bond lengths and geometry’s. To provide sufficient surface area for encapsulation of the PMOS4 chip, there is a 16 x 16mm dispense area in the centre of the board. This area is free of solder mask, enabling the encapsulant to adhere directly to the FR4 or BT. In addition to encapsulating this area, the encapsulant also covers the edge of the solder mask.
To enable external biasing of the corrosion monitors during testing, plated through-holes were located on the board. PTFE coated multi-strand flex was soldered to these through-holes. Biasing consisted of centre track ground and the outer tracks biased ( 5 volts. As a precautionary measure in case of short circuits in the corrosion monitors, surface mount current limiting resistors of 10 K( were placed in series with the ( 5 volt bias lines.
The overall dimension of the test board was 43 x 44mm. This board provides 34 edge connector measurement points which can be connected to a multiplexing test station and also a further 26 points which were easily probed. All these test points made it possible to track individual failure locations that occur in the daisy chains.
Characterization of the Material Set
To complete the packaging assembly on the test board, firstly the test die must be placed on the board using a die attach adhesive, the next stage of the process involves the wire bonding using gold or aluminum before finally encapsulating the wire bonded die using the liquid encapsulants under investigation. To ensure a repeatable and optimum assembly run it was imperative that all materials and processes be characterized prior to the dispensing on the test boards.
Die Attach
To investigate the die attach to be used in the project, a number of die similar to that used in the evaluation were placed on glass slides and on FR4. The glass slides allowed for a visual inspection of the underside of the die after curing. A number of different patterns were then investigated to optimize the pattern for the die attach/die size being used. This pattern was then laid down on FR4 and the die placed on these samples. These samples were then micro-sectioned and investigated using scanning acoustic microscopy (SAM) to yield the optimum die attach pattern and dispense parameters.
Die Placement
Die were placed on the test boards using a repeatable process to ensure each die had the complete underside coverage, minimum bleed-out and a sufficient bond line thickness. Placement of the PMOS 4 chip was accomplished by means of a Finetech flip-chip die placement and bonding instrument. Although normally used for flip-chip assembly the machine is also used for accurate and repeatable die placement for conventional die attach processes. This instrument enables the optical alignment of the chip to within 0.25mm. Another feature of this instrument is the ability to apply a uniform and repeatable pressure on the chip thus ensuring consistency for all chip attachments.
Die Adhesion Strength
For the die attach to offer sufficient strength it is necessary that it has a bondline thickness of approximately 25 microns. It is also imperative that voids be kept to a minimum, if not eliminated completely, as excessive voids may reduce bond strength. The die attach used was Ablebond 8322A, which has a proven record for successful die attach of large area die. It is flexible and cures quickly resulting in less thermal degradation of the boards. It also exhibits minimal resin bleed-out and low condensable volatiles.
Stress Elimination
After encapsulation the completed packages experienced a wide variety of tests (temperature cycling, temperature/humidity, etc.) and it was essential that the die attach survive these processes. As a result of these tests the packages experienced increased package internal stress, which may cause physical damage to the mechanical assembly of the package. A primary reason for selecting this die attach was its good stress absorption characteristics to pass such tests, in particular when using a die of area 10x10mm. This choice of die attach minimizes the effect of die attach on the assembly reliability ensuring that it is the encapsulant which is being primarily evaluated.
Encapsulation
As there was a large variation in the material types and properties that were being investigated (epoxy/silicone, viscosity/hardness, etc.) it was imperative that each material was dispensed and cured at optimum conditions to ensure that the material performed to its best. To establish the optimum dispensing parameters each material was characterized prior to the final dispense on the test boards. This involved investigating such parameters as:
Needle diameter
Dispense pressure
Speed of dispense head
Height of needle above test board
Pattern of dispense
Line width
Vacuum level
Substrate heating
These parameters were investigated with a view to achieving the best encapsulation for the IC and as a result of using the optimum cure and dispense schedule to achieve:
Void free encapsulation
Sufficient die and wire bond coverage
Dam heights (if applicable)
Dispense Pressure, Speed, Line Width and Needle Diameter are parameters which were varied until a sufficient amount of encapsulant was dispensed to protect the die and wire bonds, at an acceptable speed and to ensure that wire bond sweep did not result from the encapsulant flow.
While pattern of dispense is also related to the sufficient coverage of the die, it plays a larger part in the entrapment of voids at the edge of the die and under the wire bonds, it was found that the spiral-in pattern performed best in all cases. It was also observed that the majority of materials performed better when the substrate was heated between 40–70oC in order to minimize the formation of voids and ensuring that the material would flow into the fine gaps, which is of critical importance with regard to wire bond coverage and reduced wire bond sweep thus resulting in a more robust assembly.
Samples were also put under a vacuum to remove any entrapped air before curing. Where necessary certain silicone encapsulants had to be transferred to syringes for dispense and these received extensive degassing prior to dispense, to ensure that voids were not dispensed within the encapsulant. Where applicable, dam materials were also investigated to achieve optimum dam thickness and height.
To investigate the above parameters, test die were placed on samples of substrate which were then encapsulated using the various encapsulants that were under investigation. With each encapsulant, test parameters were varied until the optimum parameters of the material were achieved. These samples were then investigated by SAM and by microsection to ensure that the encapsulants offered sufficient protection.
All encapsulant samples were cured at the manufacturer’s recommended cure schedule and unless otherwise specified ramped up at 2oC per minute.
Popcorn Testing
After all the materials and encapsulants, the test boards were put through a series of environmental tests including HAST, temperature cycling, thermal overstress and popcorn testing. This paper will only report on the results of the popcorn test.
Moisture inside a package turns to steam and expands rapidly when the package is exposed to the high temperature of VPR (vapor phase reflow), IR (infrared) soldering, or, if the package is submerged in molten solder, wave soldering. Under certain conditions, the pressure from this expanding moisture can cause internal delamination of the encapsulant from the chip and/or substrate, internal cracks that do not extend to the outside of the package, bond damage, wire necking, bond lifting, thin film cracking, or cratering beneath the bonds. In the most severe case, the stress can result in external package cracks. This is commonly referred to as the “popcorn” phenomenon because the internal stress causes the package to bulge and then crack with an audible “pop.”
For EIA/JEDEC standard, test method A122A, in accordance with EIA/JESD22-A112-A, samples were electrically tested and scanned using a Scanning Acoustic Microscope. The samples were then baked dry at a temperature of 125°C for 24 hours. Test level 1 required samples to be exposed to Temperature/Humidity of 85°C at 85%RH for a period of 168 hours.
Following this, samples were again electrically tested to ensure wire-bonds remained intact. Within 4 hours of leaving the temperature/humidity chamber, the samples were passed through an IR Reflow Oven for three cycles with the following profile.
- Ramp-up rate+6°C/second max
- Temperature maintained at 125(±25)°C 120 seconds max
- Temperature maintained above 180°C 120-180 seconds
- Time at maximum temperature 10-40 seconds
- Maximum temperature 220+5/0°C
- Ramp-down rate-6°C/second max
Each sample was passed through the IR reflow oven three times and then electrically tested and scanned using a Scanning Acoustic Microscope. Two different techniques were used to determine the extent of delamination, Through transmission scanning and C-Scan. The pulse-echo C-Scan is a depth -specific technique. The transducer is focused on a specific interface and returns amplitude and phase information for that interface. Phase inverted areas, normally indicating delamination, are displayed as red. Any voids above the interface of interest will block transmission of the sound waves and will be displayed in black.
Through transmission scanning is used for evaluating the entire volume of the sample in one scan. This approach requires acoustic access to both sides of the sample. Ultrasound is transmitted from the transmitter transducer to the receiver on the other side of the sample. As ultrasound cannot penetrate air any voids/delaminations will be displayed as black. It is useful for fast determination of internal structure, including defects, but it does not generally provide depth information about a particular feature or defect, i.e., it will tell you if you have a problem/delamination in your sample but not where it is in the sample.
Analysis of the globtop samples is performed by taking pulse-echo and through transmission images of all the samples before and after the popcorn tests. The images are then compared against each other.
Results
Figure 6 shows SAM images from sample A, before and after popcorn testing.
The SAM images are laid out as follows :
Three samples of each encapsulant were put through the popcorn test. All samples tested showed substantial delamination at the die/encapsulant interface as seen in Figure 6. This constitutes a failure according to EIA/JESD22-A112-A and so all of the encapsulants are deemed to have failed the test. Many of the samples also displayed significant external cracking. The number of broken wire bonds in each sample was also counted and tabulated in Table 2 below. Since all of the encapsulants failed the test, the number of broken wire bonds serves as a comparison between them to determine which of them performed better. All of the daisy-chains under Material A remained intact making it by far the best performer. Of the other seven glob-tops the number of broken wire bonds ranged from 3 up to 64 out of a maximum of 192. For the epoxies, reliability varied between materials with FR4 or BT substrate and with aluminum or gold wire bonds. Gold wire bonds and BT substrates show a significant reduction in wire-bond breakages when encapsulated by silicones. However, the least number of wire-bond breakages are observed when the silicones are encapsulating FR4 boards and gold wire bonds. Two encapsulants, materials E and G had wire-bonds broken even before passing through the IR oven.
Conclusions
This paper has presented the results of popcorn testing on eight commercially available encapsulant materials, both epoxies and silicones. None of the encapsulants passed Jedec Level 1 testing, showing severe die/encapsulant delamination in all cases. Material A provided the best wire bond protection with none of the 192 wire bonds failing. It is unfortunate that no material passed the test. While it is at the top of the severity scale, a material which could provide stability in these conditions would be advantageous. Further work needs to be done testing these materials to Jedec Level 2, 3, etc., to determine the level of moisture resistance that each can provide.
References
- J.W. Balde, “The effectiveness of silicone gels for corrosion protection of silicon circuits,” IEEE Trans. Comp., Hybrids Manufact. Technol., vol. 14, pp. 352-356, June 1991.
- J.A. Emerson et al., “HAST evaluation of organic liquid IC encapsulants using Sandia’s test chips,” in Proc. 1992 Electron Comp. Technol. Conf. (ECTC), 1992, pp. 951-956.
- R. Doyle et al, “Glop-top reliability Characterisation: Evaluation and Analysis Methods,” IEEE Trans. Comp., Pack. and Manufact. Tech., vol. 21, pp. 292-300.
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