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Advancing Microelectronics • Volume 28, No. 2 • March/April 2001

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Study of DC/DC Converters in High-Performance Processor Power Delivery Systems

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Shamala A. Chickamenahalli, Yuan-Liang Li, and David G. Figueroa

Abstract:
     With the advances in MOSFET technologies, switching a dc/dc converter at several MHz has become rather common. Also multiple phases of these converters are required in order to meet the increasing transient power requirements of the load. In this paper, the application of a multiple-phase, full synchronous dc/dc converter model when connected to a microprocessor power delivery system is addressed. Performance evaluation of the complete power delivery system based on a single and four-phase dc/dc converter is done. Advantages and disadvantages of each design are noted. Comparison is also made for various load representations. The load representations considered include a piecewise linear current source, a time-controlled switch, and a first and second-order polynomial voltage controlled current source. Differences in the output characteristics with a simple source replacement of the dc source and with an actual VRM are also highlighted.
     Key Words: Power Delivery, Converters, VRM, Filters, Capacitors

I. Introduction
     Voltage regulator modules (VRM) that are an integral part of the power processing stages beyond the silver box have undergone tremendous growth. Compared to a decade ago, the emphasis to share the efforts in power supply development has been noticeable more than ever. These advances have been possible because of the technological advances in MOSFET and other device technologies, processes and improvements in their switching frequencies. The reduction in sizes of devices has also lead to several approaches in the integration of control and power circuits. Several VRM topologies have been studied for the specific application in microprocessors [1-3]. Buck converter with a synchronous rectifier has been the best candidate for the VRM’s of microprocessor power supplies for a long time [4]. Studies on topologies of synchronous buck converters fed from 12V is reported [5]. Analysis when the VRM is fed from a 5V input is also available [3].
     On the other hand, the operating voltage of microprocessor CPU’s has constantly declined and may be below 1V in the near future. The current levels may exceed 100A at the output of a VRM soon. Of the breakthroughs in this direction, noticeable is the urge to enhance the switching frequencies of VRMs from current few hundred’s of kHz to several MHz. In addition, adopting more than one phase for conducting the increased currents is one recent approach. The effective advantage of increasing the number of phases is a drastic reduction of VRM filter element sizes and reduction in the response time of the VRM. Due to multiple phases conducting over any cycle, the ripple current is also reduced at the output of the VRM. Several attempts wherein enhancing the switching frequencies to 2MHz/ph and up to 10 phases are seen. Studies relating performance while paralleling several phases of converters have been reported [6-8]. Experimental work has predicted the efficiency attainable in these configurations [6]. At the same time, achieving the efficiencies in the 90% range remains as the next biggest challenge.
     Application of a switching power converter in the power supply scheme of an Intel microprocessor is the subject of this paper. A multi-phase VRM model and its design considerations are given in Section III. Power model performance when fed with a simple voltage source and an actual four-phase switching VRM power source is discussed in Section IV. Comparison is made of the effect of different die load representations. Also responses of a single-phase VRM and a four-phase VRM are studied. The input voltage of 12 V is chosen in our analysis.

II. Lumped Model of a Power Delivery System
     Fig. 1 represents the lumped power model of an Intel microprocessor. The various loops represent the stages of package and interconnects. The model elements actually are interconnect element parameters and their parasitics. The first and second level of decoupling is provided by the capacitors Cpkg and Cint. The die can be represented in several ways. A voltage controlled current source representation G is shown here. The battery in series with an inductor and a capacitor across the combination serves as a simple source to the power model. A switching power supply marked ‘Powerpod’ in Fig. 1 replaces this simple source for the case of a complex power source. The integral component of the switching supply is the voltage regulator module (VRM). The VRM attaches to the rest of the power delivery system via a connector. The processor voltage Vcc is monitored across the nodes 3 and 2 across Vdd and Vss monitor points. The die voltage monitored across nodes 6 and 7 is utilized to determine if the circuit meets transient droop voltage specifications. The lumped circuit model when fed with the simple source is a passive circuit whose analysis is straightforward. Whereas, with the VRM as the input stage, the circuit becomes an active circuit as it involves feedback control (voltage across points marked ‘voltage feedback point in Fig 1) and suitable timing strategies for the switches. In the next section, a brief description of a VRM model along with its design considerations is provided.

III. VRM model
     Fig. 2 (a) represents the equivalent circuit of a VRM model [1-3]. The topology is a buck type wherein the main switch S1 enables the step down of the input voltage. Lf and Cf constitute the low pass output filter elements. The duty ratio D of the converter is the ratio of the input voltage Vin and the output voltage V0. Switch S2 conducts at all other times when the main switch S1 is off. Thus the current IL in the inductor Lf varies between values of Imax and Imin as shown in Fig 2(b). VRM switching frequency fs pertains to the rate at which the two switches are switched. The switch S2 can be a fast diode or a MOSFET. When the switch S2 consists of a MOSFET instead of a diode, the configuration represents a synchronous rectifier topology. Eref is the voltage whose value is to be maintained across the monitor points as Vcc in any power model. It serves as one of the inputs to a comparator inside the controller that implements both voltage and current feedback.

(i) Multi-phase VRM
     Multi-phase VRMs as mentioned earlier have become the norm of modern switching power supplies due to the several advantages in terms of cost, size and response characteristics achievable. Fig. 3 shows the block diagram of a four-phase VRM without the detailed control and driver circuitry. A multi-phase VRM consists of several phases in which each phase is made to conduct for an equal part of each cycle. Within each phase, the two switches conduct in the same manner as described in the basic converter. Each phase consists of a per-phase inductor. However a single bank of bulk capacitors is used at the output point where all the phases combine. The switching signals for the main switches of the four-phase VRM are shown in the top picture of Fig 4. The steady-state currents that result in response, in the four VRM phases are shown in the bottom of Fig 4.

(ii) VRM Design Considerations
     The magnitude of the current a VRM has to supply, the magnitude of current change in the inductor, voltage at which the current is supplied, voltage regulation at any load, and the amount of voltage ripple allowed determine the VRM inductor and capacitor values. The frequency at which the VRM is to be switched and the number of phases are additional inputs for a multi-phase design. The VRM is most commonly designed with a 5% voltage regulation ((V0) and 1% ripple voltage ((V0) specification. The phase current ripple ((IL) of the VRM is considered to be 20% of its average value. The VRM per phase inductance, bulk capacitor and the maximum ESR based on the above considerations are given by Eqn(1).

(1)

     Both the VRM inductance and the bulk capacitance values vary inversely with the switching frequency. A comparison of the inductances and capacitances of the VRM for a single and four-phase design is made in Table I.

     It can be observed from Eqn (1) and Table I that it is advantageous only if both the switching frequency and the number of phases are increased such that the size reduction advantage of is really achieved. Equally important to the design of the VRM is the cost attributed by the VRM bulk capacitors. It is usual that the available capacitors have higher ESRs for higher capacitance values. At any time, the maximum value of the ESR calculated per Eqn.(1) should not be exceeded in order that the design considerations are met. This requirement is invariably met by using several legs of identical capacitors matching the equivalent ESR to less than the maximum. Alternatively a graded response from the VRM is obtained by using several legs of capacitors of varying capacitance. The leg with the smallest RC time constant responds to supply the required current and gradually transfers control to those with the highest time constant.
     The magnitude of the current that a VRM has to supply also determines its transient requirement. The initial or the initial rate of application of the load current is effectively met by the interconnect and package stages. The minimum theoretical response time of the VRM is given by Eqn. (2)

     where (I is the change in converter output current, (V is the change in the voltage across the inductor and Lf is the inductor value.[4]. As an example, if Vin=12V, Vo=1.25V, and the current in a 50nH inductor varies between 72A and 97A, then (V=12-1.25=10.75V, (Io=97-72=25A. The theoretical response time of the VRM in such a case is 116ns.

IV. Simulation Results
     Extensive simulations are done to study the VRM model performance. The simulations are carried out on Pspice A/D. First a study with the simple VRM model when fed with a fixed voltage source is presented. The simple VRM model consists of a simple battery in series with a small resistance and an inductance. A bulk capacitor is held across this combination. Then the droop study with the complex VRM model serving as the power supply to the model is presented. Also comparison is made of the data when a single-phase and a four-phase VRM supply the input power to the circuit.

(a) Comparison of Simple and VRM Models
     A transient current load is applied at the die in order to study the voltage droop characteristics. The waveform of the voltage Vdie across the die of Fig. 1 for both the simple source and a four-phase VRM as sources is illustrated in the bottom traces of Fig. 5(a). The top trace is of the voltage Vcc measured after the power POD connector in Fig. 1. The voltage droop target for both cases is 10% below Vcc. Three droops are expected in the waveforms corresponding to the package-die, interposer-package and VRM-interposer loops. In the waveforms that pertain to the complex VRM case, the VRM feedback control loop responds and the voltage begins to rise to the required Vcc value after the third droop. Whereas in the simple source case, the voltage continuously decreases as there is no control and hence a third droop is not seen. The first droop voltage is 1.133V and 1.130V and the second droop voltages are 1.164V and 1.163V and third droop voltage for the case with VRM is 1.158V. This means that for the first & the second voltage droops, no significant difference between using a simple VRM model and a four-phase VRM. A comparison of the transient response of the VRM that feeds the power model of Fig.1 is illustrated in Fig. 5(b) where the current supplied at the die and the current in the connector which is the sum of all VRM phase currents are shown. The current level achieved from a simple VRM is comparatively lower than the current level achieved from a four-phase VRM model that explains the constantly decreasing voltage in the simple model in response to the load transient.

(b) Comparison with Single and four-phase VRM models as Sources
     A 250kHz single-phase and four-phase, 1MHz/ph VRMs whose design values were provided in Table II were tied as inputs to the lumped power model. The waveforms of the voltages across the die and after the power POD connector are shown in Fig 6(a). The currents at the output of the VRM and at the die are shown in Fig 6(b). As can be observed, the response time of the four-phase model is much smaller than that of the single-phase model due to its much smaller inductance per phase and the much lesser bulk capacitance. Similar observation can be made on the current response. The single-phase VRM provides a slow and flat transient response to the load than the four-phase VRM. Also a comparison of the droop voltages obtainable in the four-phase and single-phase cases are shown in Table II in which the ideal case entries are from the previous section.

     From the second droop data in Table II, we can observe that the single-phase VRM design is not as effective as the four-phase VRM design for this power delivery system.

(c) Comparison with different die load representations
     The effect of different die representations is also investigated. The droop voltage values and obtained currents at the die and at the edge connector with a single and double order voltage controlled current source G representation of the die and with an ideal piecewise linear current source Ipwl are represented in Fig 7. The voltage across the die nodes 6 and 7 and a piecewise linear voltage source across nodes 10 and 0 constitute the elements of second order polynomial G source. As can be observed, the difference between a single-order polynomial and the piecewise linear case is not great as compared to the double-order polynomial case. It can be concluded that a piecewise linear representation predicts the droops more pessimistically than the other two due to the current level achieved from a piecewise linear representation is comparatively higher than the current level achieved from the other two representations. With the simple source case, there is no difference in the droop waveforms when the load was a single-order polynomial representation, a double-order polynomial representation, a piecewise linear or a time-controlled switch representation. The waveforms overlap each other.

V. Conclusion
     Study of the application of a synchronous rectifier type of buck converter in Intel microprocessors is presented. A 4-phase VRM model and its design considerations are provided. A comparison of a simple ideal voltage source and a 4-phase VRM is given. In the waveforms that pertain to the complex VRM case, the VRM feedback control loop responds and the voltage begins to rise to the required Vcc value after the third droop. Whereas in the simple source case, the voltage continuously decreases as there is no control and hence a third droop is not seen. The simulated voltage droops demonstrate that for the first & the second voltage droops, no significant difference between using a simple VRM model and a four-phase VRM. A comparison of the transient response of the VRM that feeds the power model of Fig.1 is illustrated in Fig. 5(b). The current level achieved from a simple VRM is comparatively lower than the current level achieved from a four-phase VRM model that explains the constantly decreasing voltage in the simple model in response to the load transient.
     A 250kHz single-phase and four-phase, 1MHz/ph VRMs were tied as inputs to the lumped power model. The waveforms of the voltages across the die and the currents at the output of the VRM were examined. The current waveforms clearly show that the single-phase VRM provides a slow and flat transient response to the load than the four-phase VRM. Also a comparison of the second droop voltages was given in Table II. We can observe that the single-phase VRM design is not as effective as the four-phase VRM design for this power delivery system.
     A piecewise linear, a single-order polynomial, and a double-order polynomial die load representations are considered in the power delivery analysis using a complex VRM model. The analysis result shows the piecewise linear representation predicts the droops more pessimistically than the other two due to the current level achieved from a piecewise linear representation is comparatively higher than the current level achieved from the other two representations. With the simple source case, there is no difference in the droop waveforms when the load was a single-order polynomial representation, a double-order polynomial representation, a piecewise linear, or a time-controlled switch representation. The waveforms overlap each other.

Acknowledgments
     The authors would like to thank their Manager, PR Patel for his support of this work. The authors would also like to thank their colleagues Michael T. Zhang, James Dinh, and Ed Stanford for useful discussions.

VI. References
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(2) Xunwei Zhou, Xingzhu Zhang, Jiangang Liu, Pit-Leong Wong, Jiabin Chen, Ho-Pu Wu, Luca Amoroso, F.C. Lee and Dan Y. Chen, ‘Investigation of Candidate VRM Topologies for future microprocessors,’ Applied Power Electronics Conference and Exposition, 1998. APEC ‘98, pp. 145-150.

(3) Pit-Leong Wong, F.C. Lee Xunwei Zhou, Jiabin Chen Xingzhu Zhang, ‘VRM Transient study and output filter design for future processors,’ Applied Power Electronics Conference and Exposition, 1998. APEC ‘98, pp. 410-415.

(4) Todd M. Sherman, ‘Powering today’s new generation microprocessors,’ Application note, Cherry Semiconductor Corporation.

(5) Xunwei Zhou, Bo Yang, Amoroso L., Lee F.C., Pit-Leong Wong., ‘A novel high-input-voltage, high efficiency and fast transient voltage regulator module-push-pull forward converter,’ Applied Power Electronics Conference and Exposition, 1999. APEC ‘99, vol. 1, pp. 279-283.

(6) Xunwei Zhou, Xu Peng, F. C. Lee, ‘A high power density, high efficiency and fast transient voltage regulator module with a novel current sensing and current sharing technique,’ Applied Power Electronics Conference and Exposition, 1999. APEC ‘99, vol. 1, pp. 289 - 294.

(7) M. M. Jovanovic, David E. Crow, Fang-Yi Lieu, ‘A Novel, low-cost implementation of ‘Democratic’ load-current sharing of paralleled converter modules,’ IEEE Transactions on Power Electronics, Vol.11, No. 4, July 1996. pp. 604-611.

(8) Cheng D.K.W., Liu X.C., Lee Y.S., Hom Hung, ‘Parallel operation of DC-DC converters with synchronous rectifiers,’ Power Electronics Specialists Conference, 1998. PESC 98 Record. 29th Annual IEEE, pp.1225-1229(vol.2) pp. 410-415 (vol.1).