Developing the Next Generation Wireless Terminals: Challenges for Packaging and Substrates
Petri Savolainen, Nokia Mobile Phones, Itmerenkatu 11-13, 00180 Helsinki, Finland, Tel. +358 7180 39382, e-mail petri.jo.savolainen@nokia.com
Abstract
It has been estimated that within a few years there will be more wireless terminals connected to the Internet than fixed line equipment. Consequently, the wireless terminal will transform from voice-mainly device to a multifunctional device. The wireless terminal must have very high performance and high functionality combined with small size, high reliability and low energy consumption. Hence, there is a dire need for cost effective, high-density, high performance packaging and substrate technologies that enable designers to achieve the targets.
Numerous novel miniature IC packages have been developed recently, including variants of Chip Scale Packages (CSP) and Direct Chip Attachment (DCA). A growing trend is stacked or 3D packages with two or more ICs on top of each other inside the package. With diminishing component sizes and pitches, the Printed Wiring Board (PWB) has to evolve towards higher tracking densities. The PWB industry is actively developing technologies to offer solutions for higher density needs.
Introduction
The wireless terminal is becoming an information and entertainment center for the consumer and it will serve as the mobile office for the business user. It should provide connectivity regardless of user location and enable the user to utilize the services she/he has subscribed. The wireless terminals will need very high performance and high functionality combined with small size and low energy consumption, naturally keeping in mind the cost and reliability. This is especially true for the Universal Mobile Telecommunication System (UMTS) terminals, which will offer high data rates for wireless connection, varying from up to 384 kb/s when moving to 2Mb/s for office environment.
Traditionally, the-smaller-the-better has been the trend in the wireless terminal business, i.e. smaller terminal with equal functions will sell better than its larger counterpart. The developments in wireless terminals’ size and weight can be seen in Fig. 1. An additional aspect for the future wireless terminals is the performance, which increases the complexity of the task in hand. In order to achieve the expectations for the performance, there is a need for high-density, high performance packaging and substrate technologies.
Many new IC packages have been developed recently, including variants of the CSP family as well as DCA. These packages utilize small solder joint pitches, down to 0.5 mm with CSPs and 0.12 mm for DCA (Flip Chip). Parallel with the transfer to smaller interconnection pitch has been a move from peripheral pin layout to area array layout. This is especially true for CSP-type package technologies, and to some extent for DCA (Flip Chip). With diminishing component sizes combined with increasing number of such fine pitch components, the substrate or the printed wiring board (PWB) is facing new challenges.
Conventional multilayer PWBs have difficulties in handling the routing requirements of the latest wireless terminals and usually with a cost penalty. Therefore, the PWB industry is developing technologies that achieve minimum via size for connecting layers as well as reduce effectively the line width and space between the lines. By these measures, the routing capability of PWB can be increased, but again with some cost disadvantage. However, the designer and manufacturer of the terminal should not only consider cost per unit area but cost per function, trying to optimize the total system cost to a level that is acceptable to the end customer and to the manufacturer.
Packaging Technology
CSP is a packaging technology family that by definition should be robust to facilitate easy handling, testing and assembly. The CSP offers a small package with very thin profile and performance close or equal to that of DCA. Ideally, the CSP can be handled with standard fine-pitch surface mount assembly equipment, which means that it can be adopted to production without additional investments to assembly line. Area array pin pattern allows redistribution of peripheral chip pad layout to coarser pitch. Moreover, chip downsizing does not affect the package footprint when using interposer CSPs. Conventional packaging processes and materials are applied to many CSP packages.
In many cases the users of the CSP technologies are using underfill or in some cases mechanical support to increase the reliability. Using underfill adds process and material costs as well as decreases the throughput. The mechanical solutions increase the cost of the product and also add to the weight. In order to eliminate the need to use underfill or mechanical support structures, package, substrate, and assembler should work together to find the optimal solution.
DCA offers the smallest possible component size, providing good electrical performance. Pads can be arranged in array pattern by using a redistribution layer on the IC enabling high pin counts. Therefore, DCA is a feasible way to achieve a high density, small outline packaging solution. One of the key issues to fully utilize the DCA benefits is to design the IC in such a way that pads are arranged in a format that allows use of area array bump pattern with relaxed pitch.
Before DCA will be fully utilized in volume production there are some barriers to overcome. Known Good Die is evidently one of these: a substantially high IC quality and yield must be achieved before proper assembly yields at users line can be expected. Availability of bare IC with or without bumps is still limited although new players are coming into the field. Bumping process may damage the IC before final assembly and, consequently, the bumping process must be well in control to achieve high yield. In conclusion, optimized materials and processes are the key to achieve the best possible DCA quality.
Substrates
One of the biggest challenges when using the high-density packages is to find suitable cost-effective substrates. The solution is to use substrates with microvias. Microvias are mainly produced by laser drilling and photo-processes, but other methods exist.
The throughput of laser-drilling process has improved considerably and the process is economically more viable to produce high numbers of vias per square meter. Hence, since the process is similar to the mechanical drilling and equipment is available, this is the current mainstream process for microvia PWBs.
Mass generation of vias can be performed with photo-processes. The photo processes use existing materials and equipment and basically it can be utilized without major capital investments. However, the materials are slightly more complicated to use than those for the laser processes. Depending on the material developments the photo via technologies may gain popularity in the future.
The current trend is towards technologies that allow placement of the vias anywhere the designer wants. Examples of such are ALIVH and B2it technologies. The former utilizes laser drilling for the via formation and the vias are filled with conductive paste. When the layers are pressed together the paste is compressed and forms conductive path between metal layers. In B2it the vias are formed by screen printing conductive paste on copper foil. The paste forms cones that are hardened by curing the paste, and consequently the paste “spikes” push through the dielectric layers forming contact between the metal layers.
Whatever technology is chosen, materials meeting the processing and end-use requirements have to be available. The processing properties of the materials should enable high yield production with minimum waste generation in the PWB factory. Minimum twist and bow are required at the assembly line for maximizing the yield. Furthermore, the properties of the materials must meet the electrical and thermal performance requirements in the use environment and the materials must survive the planned life cycle of the product without changing their properties.
Concluding Remarks
As the wireless terminals change gradually to personal, be connected everywhere anytime devices, the requirements for packaging and substrate solutions increase rapidly. New materials and technologies are needed along evolution of the existing technologies. The situation becomes more challenging because the increased performance and small size should be available with lower price, yet with very high reliability.
The packaging solutions evolve around the CSP packages and to some extent Flip Chip. Additional boost will be achieved with the 3D or stacked packages, especially if the z-dimension can be kept as small as possible. One of the major challenges is the thermal performance of the new packages, since the power will be in a much more concentrated area than before.
The substrate technologies are evolving towards solutions that meet the requirements of the improved packages. More work is still needed to improve the reliability and cost for the PWBs. Additional gain can be achieved if the embedded passive components can be realised in to the organic substrates.
Although the new technologies are currently more expensive than the mainstream they should in the long run reduce the total system cost to the original equipment manufacturer or contract manufacturer. This will come from the reduced usage of materials, modularity and improved time-to-market.
Petri Savolainen received MSc. and Dr. of Technology degrees in materials science from Helsinki University of Technology in 1991 and 1996, respectively. His research subject was anisotropically conductive adhesives for display and Flip Chip applications. He was a member of the research team that developed solder-particle filled ACAs at Helsinki University of Technology. Since 1996, he has held engineering and engineering manager positions at Nokia, currently at Nokia Mobile Phones. His work involves miniaturisation of wireless terminals, including such areas as advanced PWBs and IC packaging as well as displays, camera modules, and mechanics. He is a member of IEEE-CPMT and IMAPS.
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