The Instructor:
Dr. Zweben, an independent consultant, has directed development and
application of advanced packaging materials for over 30 years. For many
years, he was Advanced Technology Manager and Division Fellow at GE Astro
Space, later acquired by Lockheed Martin, where he directed the Composites
Center of Excellence. Other affiliations have included DuPont, Jet Propulsion
Laboratory and the Georgia Institute of Technology NSF Packaging Research
Center. Dr. Zweben was the first, and one of only two winners of both
the GE One-in-a-Thousand and Engineer-of-the-Year awards. He is a Fellow
of ASME, ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished
Lecturer for AIAA and ASME. He has published and lectured widely on advanced
thermal management and packaging materials.
Flip Chip Assembly – PDC2
Instructor: R. Wayne Johnson, Auburn University
Course Description:
Flip chip use is growing in both flip chip-in-package and flip chip-on-laminate
applications. This course will provide insight into the design and assembly
of electronics using flip chip devices. The practical issues of implementing
flip chip technology from wafer bumping to reliability characterization
are covered. This course will begin with an examination of bumping options
and corresponding design rules. Redistribution will also be discussed.
Substrate requirements for flip chip will then be presented including
a discussion of high density interconnect options and substrate design.
Assembly of flip chip devices adds materials and processes to the standard
SMT assembly process and the integration of these into the SMT process
flow is examined. Materials and processes to be discussed include lead
free alloys, fluxes, underfills (capillary flow, fluxing no-flow, and
wafer applied), substrate dehydration, flux and underfill application,
underfill curing, inspection, and underfill characterization techniques.
The presentation will conclude with a discussion of flip chip assembly
reliability testing, test vehicle design and failure analysis.
The Instructor:
Dr. Johnson is an Alumni Professor of Electrical Engineering at
Auburn University and Director of the Laboratory for Electronics
Assembly and
Packaging (LEAP). At Auburn, he has established teaching and
research laboratories for advanced packaging and electronics
assembly. Research
efforts are focused on materials, processing, and reliability
for electronics assembly. He has worked in MCM design, MCM-L,
-C and -D substrate technology
as well as advanced SMT, wire bond and flip chip assembly techniques.
He has published and presented numerous papers at workshops and
conferences and in technical journals. He has also co-edited
one IEEE book on MCM
technology and written two book chapters in the areas of silicon
MCM technology and MCM assembly. He received the 1997 Auburn
Alumni Engineering
Council Senior Faculty Research Award for his work in electronics
packaging and assembly.
Dr. Johnson was the 1991 President of
the Society. He received the 1993 John A. Wagnon, Jr. Technical
Achievement Award from ISHM,
was named
a Fellow of the Society in 1994 and received the Daniel C. Hughes
Memorial Award in 1997. He is also a member of IEEE, SMTA,
and IPC.
Dr. Johnson received the B.E. and M.Sc. degrees in
1979 and 1982 from Vanderbilt University, Nashville, TN, and the
Ph.D.
degree in 1987
from Auburn University, Auburn, AL, all in electrical engineering.
He has worked in the microelectronics industry for DuPont,
Eaton, and Amperex.
Hermeticity Testing and Issues with RGA - PDC3
Instructor: Thomas J Green, Microelectronics Packaging Consultant
Course Description:
Hermeticity of electronics packages and hermeticity test techniques
continue to be of critical importance to the microelectronics packaging
community. Specifically, in the area of MEMS/MOEMS packaging, OLEDs,
wafer scale packaging, optoelectronic devices and packaging for Military
and Space. In addition, there are a host of medical implants, bio medical
devices and emerging nanotechology applications that all require hermetic
packages and valid techniques to measure the leak rate. This course begins
with an overview of hermetic sealing processes e.g. seam welding (also
know as brazing), laser welding; solder sealing and techniques/methods
to seal components at the wafer level.
The class will then examine the accepted leak test techniques
as prescribed in Mil Standard 883 Test Method 1014. This misunderstood
test method
is often a source of frustratio. The basic science behind helium
fine leak testing (both the fixed and flexible methods) will be presented
to the
class along with the advantages and potential pitfalls of helium
fine leak testing. Difficulties and limitations in fine leak testing
of
small volume
packages is a major industry concern, especially among the Space
community. Issues with bomb times and pressures, measured leak rate
vs air leak rates, “one
way leakers”, virtual leakers will be addressed, along with gross
leak testing; bubble, weight gain and other techniques such as
dye penatrant. In each case the focus will be on practical issues
facing the industry.
The Instructor:
Mr. Green is a consultant and adjunct professor at the National Training
Center for Microelectronics. At NTCm he designs curriculum and teaches
industry short courses relating to advanced microelectronics manufacturing
processes. He has over twenty years experience in the microelectronics
industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At
Lockheed he was a Staff engineer responsible for the materials and manufacturing
processes used in building custom high reliability space qualified microcircuits
(Hybrids, MCMs and RF modules) for military and commercial communication
satellites. Tom has demonstrated expertise in seam sealing and leak testing
processes. He has conducted experiments and presented technical papers
at NIST and IMAPS on leak testing techniques and optimization of seam
welding processes through statistical DOE methods. At Rome Labs he worked
as a senior reliability engineer and analyzed component failures from
AF avionic equipment along with providing technical support for a variety
of Mil specs and standards (e.g. MIL-PRF-38534 and MIL-STD-883). Tom
is an active member of the IMAPS and is currently the chairman of the
Optoelectronics National Technical Committee. He has a B.S. in Materials
Engineering for Lehigh University and a Masters from the University of
Utah.
Monday, March 14
Registration: 7:30 am – 7 pm
Continental Breakfast: 7:30 am
Exhibit Opens: 10 am – 7 pm
Session 1: Plenary
Chairs: Ted Tessier, ST Assembly Test Services Inc.; Andrew Strandjord,
IC Interconnect
8 am – 12:30 pm
Developments and Trends in 3D Packaging
Flynn Carson, ChipPAC, Incorporated
Wafer Bumping
Peter Elenius, E &G Technology Partners LLC
Break in Exhibit Hall: 10 am – 10:30
am
Wafer Level MEMS Packaging Strategies
Daniel Baldwin, Engent, Inc.
WLCSP Technology Direction
Michael Toepper, Fraunhofer IZM
Lunch in Exhibit Hall: 12:30 pm – 1:30
pm
Session 2: Design/Modeling
Chairs: Christo Bojkov, Texas Instruments; R. Wayne Johnson, Auburn
University
2 pm – 5:25 pm
Superior Electrical Properties of High Performance Glass Ceramic Packaging
for Demanding SiGe, ASIC, Microprocessor and Advanced Server Applications
Warren D. Dyckman, Benjamin Fasano, Christopher Spring, Gary LaFontant,
IBM
Controlling Simultaneous Switching Noise with Built-in Bypass Capacitors
Narimasa Takahashi, IBM
Leading Edge Clearance Effects on Natural Convection in Parallel Plate
and Finned Metal Foam Heat Sinks
Anandaroop Bhattacharya, R. L. Mahajan, Indian Institute of Technology,
Bombay
Break in Exhibit Hall: 3:15 pm – 3:45
pm
Buoyancy Induced Convection in Metal Foam and Finned Metal Foam Heat
Sinks
Anandaroop Bhattacharya, R. L. Mahajan, Indian Institute of Technology,
Bombay
Layer Count Reduction for Area Array Escape Routing
Rui Shi, Hongyu Chen, Chung-Kuan Cheng, University of California
Evaluation of the High Frequency Transmission Properties of the Fine Wiring
Packaging Substrates Based on the 3D Electromagnetic Simulation
Masataka Yamaguchi, Satoru Kuramochi, Yoshitaka Fukuoka, Dai Nippon
Printing Co., Ltd.
High-Speed Electrical Performance of Multi-Row Lead Frame Packages
Sam Karikalan, STATS ChipPAC, Inc.
Session 3: Wafer Bumping
Chairs: Peter Elenius, E&G Technology Partners LLC; Jamin Ling, Kulicke & Soffa
Industries Inc.
2 pm – 5:25 pm
Stress in Thin Films - Fundamentals and Applications in WL CSP
Christo Bojkov, Texas Instruments
Gold Bump Technologies - Plating versus Ball Bumping
Daniel D. Evans, Palomar Technologies
Stud Bumping for Flip Chip - An Alternative Strategy
Jamin Ling, Matt Meyer, Matt Osborne, Vincent McTaggart, Kulicke & Soffa
Industries Inc.
Break in Exhibit Hall: 3:15 pm – 3:45
pm
Factors Limiting the Electrodeposition Rate of Various Bumps for Flip
Chip Interconnects
Bioh Kim, Bob Batz, Tom Ritzdorf, Semitool, Inc.
Flip Chip Bonding Enabled by Ink Jet Printing of UBM, Solder Bumps and
Underfill
Donald J. Hayes, MicroFab Technologies, Inc.
Advances in Resist Processing and Alignment Technology for Wafer Level
Packaging
Chad Brubaker, Markus Wimplinger, EV Group, Inc.
Land Grid Array (LGA) as a Pb-Free Approach for Ceramic Ball Grid Array
Packages
Linda Bal, Terry Burnette, Thomas Koschmieder, Joachim Rayos, Freescale
Semiconductor
Reception in Exhibit Hall: 5:30 pm
Tuesday, March 15
Registration: 7:30 am – 5 pm
Continental Breakfast: 7:30 am
Exhibit Hours: 9 am – 5 pm
Session 4: MEMS
Chairs: Daniel Baldwin, Engent, Inc.; Leonard Schaper, University
of Arkansas
8 am – 11:25 am
Open-Cavity IC Plastic Packages: Supporting Today's Challenges for the
Selection of the Ideal Production Package
David Hypnarowski, Ellen Emery, Bill Lawrence, Bob Blue, Quik-Pak,
Division of Delphon Industries
Active Micromachined Vibration Isolation Filters using Electrostatic Actuation
to Enhance Packaging for Mechanically Harsh Environments
Robert Dean, Ken MacAllister, Nicole Sanders, Scotte Hodel, George
Flowers, R. Wayne Johnson, Auburn University; Mike Kranz, Morgan Research
Corporation
Magnetics on Silicon using Electroplated Magnetics Materials
Sean Cian O'Mathuna, Terence O Donnell, Saibal Roy, NingNing Wang,
Paul McCloskey, Andrew Connell, NMRC
Break in Exhibit Hall: 9:15 am – 9:45
am
Near Hermetic Liquid Crystal Polymer Air Cavity Packaging for Microwave,
MEMS and Optical Applications
John W. Roman, RJR Polymers, Incorporated
Development and Characterization of Transmission Laser Bonding Technique
Jong-Seung Park, Ampere A. Tseng, Arizona State University
3-D Microsensor Modules for Future Intelligent Environments
Bivragh Majeed, John Barton, Kieran Delaney, Stephen Bellis, Kafil
Mahmood, Brendan O'Flynn, Bivragh Majeed, Andrew Lynch, Sean Cian O'Mathuna,
NMRC
Sloped Sidewall DRIE Process Development for Through Silicon Vias
Swetha Polamreddy, R. Figueroa, S. Burkett, S. Spiesshoefer, L. Schaper,
University of Arkansas
Session 5: Materials
Chairs: Scott Cummings, Dow Chemical Co.; Beth Keser, Freescale Semiconductor
8 am – 11:25 am
A Hermetic Liquid Crystal Polymer Printed Circuit Board Based Packaging
Platform for Highly Integrated Devices
Linas Jauniskis, Brian Farrell, Foster-Miller, Inc.
High Performance UV Curing Adhesive for Image Sensor Package
Yukinari Abe, Osamu Suzuki, Yuuka Soya, Junich Kaneko, Namics Corporation
Lead Zirconate Titanate Thin Films Directly on Copper Electrodes for Embedded
Passive Applications
Sudarsan Srinivasan, Angus I. Kingon, North Carolina State University
Break in Exhibit Hall: 9:15 am – 9:45
am
Impact of Material Properties and Assembly Geometry on Bond-line Stress
When Bonding PCBs to Heat Sinks with an Isotropic Conductive Adhesive
Andrew P. Collins, Emerson and Cuming
Stress Control in Thin Wafers for Backside Metal Applications
Kathy O'Donnell, N. Brings, J. Chiu, J. Kostetsky, S. Golovato, D.
Goodman, NEXX Systems Inc.
Low Temperature Curing of Polymer Films for Wafer Level Packaging
Robert L. Hubbard, Lambda Technologies, Inc.
Processing and Reliability of No Flow Underfills and the Influence of
Underfill Voids
Dan Baldwin, Engent, Inc.
Lunch in Exhibit Hall: 11:30 am – 12:30
pm
Session 6: SiP/3D Packaging
Chairs: Flynn Carson, ChipPAC, Incorporated; R. Wayne, Johnson, Auburn
University
1 pm – 4:25 pm
A Novel MEMS Based Ultra-High Density Interconnect for Wafer-Level Ultra-Thin
Die Stacking Technology
Parthiban Arunasalam, Harold D. Ackler, Sandeep Makhar, Bahgat G.
Sammakia, State University of New York at Binghamton
Electrical Performance Limitations of On-Package Decoupling Capacitors
Leonard W. Schaper, Richard K. Ulrich, University of Arkansas
Flexible and Embedded Packaging of Thinned Silicon Chip
Kyu-Ho Shin, Chang-Ryoul Moon,Tae-Hee Lee,Yong-Jun Kim, Samsung Advanced
Institute of Technology
